The present invention relates to a method of manufacturing a semiconductor device in which a semiconductor layer formed by means of selective epitaxial growth or non-selective epitaxial growth is provided on a semiconductor substrate and, more particularly, to a method of processing an opening in an insulation film on which an epitaxial growth semiconductor layer is formed.
Recently, devices have been proposed and are on the way of practical utilization in which higher speeds and higher level of integration can be achieved by forming shallow junctions, by means of low temperature epitaxial growth, in device active regions such as base regions of bipolar devices, source/drain regions and channel regions of CMOS devices. FIG. 13 is a sectional view of a semiconductor substrate on which a conventional bipolar transistor is formed, and FIG. 14 is a sectional view of a semiconductor substrate having a silicon layer selectively grown on the surface thereof which illustrates faults in a semiconductor layer. An insulation film 2 comprised of a SiO.sub.2 film having a thickness of about 100 nm or the like is formed on an n-type silicon semiconductor substrate 1. Then, an opening 21 is provided in a region of the insulation film 2 where a base region is to be formed. As a seed for the insulation film, a material which can be easily grown on a selective epitaxial growth basis must be chosen and, for example, a SiO.sub.2 film is appropriate for such a purpose. Pattern deviations can be suppressed during etching for forming the opening by employing anisotropic etching. The use of RIE (reactive ion etching) or the like results in damage in the semiconductor substrate. In this case, layers having damage must be removed by means of wet etching or the like. Next, a semiconductor layer 3 is formed in the opening 21 of the semiconductor substrate 1 by means of selective epitaxial growth that involves doping of boron (B).
The thickness of this film is about 70 to 100 nm, and the boron concentration is on the order of 5.times.10.sup.18 to 7.times.10.sup.18 atoms/cm.sup.3. A growing temperature as low as about 700.degree. C. allows a steep base profile to be formed. A selective grown layer can be grown using a gas of SiH.sub.2 Cl.sub.2 or SiH.sub.4 +HCl as a growing gas. It is preferable that edges of the selective epitaxial growth layer have a structure which does not produce facets. Next, a polycrystalline silicon semiconductor layer 5 heavily doped with p-type impurities and an insulation film (CVD SiO.sub.2 film) 6 formed using CVD (chemical vapor deposition) are stacked, and the stacked element is patterned using anisotropic etching such that the selective epitaxial growth layer 3 and the polycrystalline silicon semiconductor layer 5 overlap each other. The p-type polycrystalline silicon semiconductor layer 5 patterned by such a process is used as an extraction electrode for a base and preferably has low resistance considering a need for reducing parasitic resistance. Next, a SiO.sub.2 insulation film is grown using CVD and, thereafter, anisotropic etching is carried out on the entire surface to form a SiO.sub.2 insulation film 7 on side-walls of the pattern of the stack of the p-type polycrystalline silicon semiconductor layer 5 and the insulation film 6. The side-wall insulation film 7 has a function of determining the dimensions of an emitter as well as separating a base electrode and an emitter electrode.
For example, when the width of the pattern openings 21 is 0.5 .mu.m, the width of an emitter opening 21 can be reduced to about 0.2 .mu.m by forming the side-wall insulation film 7 with a thickness of 0.15 .mu.m. Next, an n-type polycrystalline silicon semiconductor layer 8 is formed in the openings 21, and a thermal process is performed under conditions at a level such that the temperature is 1000.degree. C.; N.sub.2 is used; and the duration is 20 sec. As a result, an n-type emitter diffusion region 31 is formed. The polycrystalline silicon semiconductor layer 8 is used as an emitter electrode (E). The p-type selective epitaxial growth layer 3 is used as a base region. The polycrystalline silicon semiconductor layer 5 is used as an external base electrode. The insulation films 2 and 6 are formed with openings to expose the underlying layer, and metal electrodes 13 and 14 are formed in contact with the underlying layer. The metal electrode 13 is used as a base extraction electrode (B), and the metal electrode 14 is used as an collector extraction electrode (C).
One of problems in the implementation of devices having active regions constituted by such a thin epitaxial layer is defects associated with leaks at junctions originating from microscopic faults produced at edges of an epitaxial growth pattern. For example, when a p-type semiconductor layer 3 is formed using selective epitaxial growth at an opening 21 of an insulation film 2 formed on an n-type semiconductor substrate 1 as shown in FIG. 14, microscopic faults (stacking faults) 32 are produced at edges of the pattern of the opening in the insulation film 2 due to the shape of the pattern edges of the opening in the insulation film 2 or due to a thermal stress or the like generated at the interface between the insulation film and the semiconductor layer. The faults 32 increase a junction leak current at leaking areas 33 at the interface between the epitaxial semiconductor layer and the semiconductor substrate, and this significantly reduces the production yield of integrated circuits. Further, selective epitaxial growth is normally accompanied by the occurrence of a facet in a semiconductor layer and, as a result, the side surface of the semiconductor layer is tapered (see FIG. 13). In this case, the problem of vulnerability to leaks at the junction between the epitaxial growth layer and the semiconductor substrate arises again because the thickness of the selective epitaxial growth layer is small at pattern edges thereof.
As a method of achieving tight contact between an insulation film and an epitaxial growth layer, a technique of forming a side-wall of an insulation film in a reverse tapered sectional configuration is known (see Jpn. Pat. Appln. KOKAI Publication No. 5-182981). According to this well-known technique, a side-wall of an insulation film is formed to have a sectional configuration which is in conformity with the configuration in which an epitaxial layer is grown. As a result, no facet is formed, and the epitaxial growth layer can be in tight contact with the side-wall of the insulation film. According to this technique, since an epitaxial growth layer is in tight contact with a side-wall of an insulation layer with no facet therebetween, it is possible to reduce leaks originating from poor jointing between an epitaxial growth layer and a semiconductor substrate due to the configuration of edge portions of the epitaxial growth layer. However, a problem still remains in that there is a need for an efficient method for forming an opening which can be efficiently used in combination with the method of forming an epitaxial growth layer.
The present invention has been conceived taking the above-described situation into consideration, and it is an object of the present invention to provide a method of manufacturing a semiconductor device comprising a novel means for processing an opening which forms an opening in an insulation film on a semiconductor substrate in a reverse tapered sectional configuration such that there is no gap between a side surface of an epitaxial growth layer formed in the opening and the opening in the insulation film.